1. Field of the Invention
This invention relates to the field of integrated circuit memories. More particularly, this invention relates to access mechanisms used for reading and writing data values within integrated circuit memories.
2. Description of the Prior Art
It is desirable within the field of integrated circuit memories that the storage density should be high thereby enabling large quantities of data to be stored. Furthermore, it is desirable that the power consumption of the integrated circuit memories should be low and their cost should be low. In order to help meet these requirements there has been a steady trend to the use of smaller device geometries. These smaller devices, such as devices based upon 45 nm manufacturing techniques, enable higher density memories to be achieved with lower power consumption. However, a problem with the use of smaller devices is that they are more susceptible to manufacturing variation whereby imperfect manufacture causes a device to differ from its original design characteristics. As an example, a transistor within the memory may be stronger or weaker than intended due to variation in its size, threshold voltage or some other parameter. This variation may result in the device failing to operate as intended and causing a failure within the integrated circuit memory. This reduces the manufacturing yield which may be achieved and makes the integrated circuit memories more expensive.
Examples of failures which can arise within integrate circuit memories include failures in write and/or read operations to individual data retention circuits (memory cells). A lack of robustness in write and read operations is becoming a significant problem in the production of high density, low power and low cost integrated circuit memories.
FIGS. 1 to 3 of the accompanying drawings illustrate three known memory cell designs seeking to improve robustness of operation. FIG. 1 shows a memory cell formed of a data retention circuit 2 in the form of a pair of cross-coupled inverters. The first inverter is formed of the transistor stack extending from Vdd to ground and comprising transistors 4, 6. The second inverter is formed of transistors 8, 10. Pass gates 12, 14 switched by a word line signal WL selectively couple the data values stored within the data retention circuit 2 on to bit lines 16, 18. The portion of the memory cell so far described corresponds to a standard six transistor (6T) memory cell. This 6T memory cell uses a small number of gates and may be readily and effectively manufactured and validated.
However, a problem with the 6T memory cell at small device geometries is that variation in the characteristics of the individual devices (transistors/gates) can result in incorrect read operation and/or incorrect write operation. As an example, a read upset may occur when seeking to read a bit value stored within the data retention circuit 2 if, as the pass gates 12, 14 are opened using the word line signal WL, the feedback within the data retention circuit 2 is insufficient to prevent an in-rush of charge from the precharged bit lines 16, 18 overwhelming the data retention circuit 2 and causing a change in the bit value stored therein. Subsequently the incorrect value would be read from the data retention circuit 2.
In order to address this problem the memory cell of FIG. 1 provides a separate read path formed of transistors 20 and 22 which selectively couple the data value held within the data retention circuit 2 to a separate bit line 24 which serves as a read bit line. Separating of the read mechanism in this way enables less conductive (“weaker”) transistors to be used as transistors 20 and 24 thereby limiting the potential in-rush of charge when a read operation is performed. This arrangement allows the bit lines 16, 18 coupled to the pass gates 12, 14 to be used only for write operations to the data retention circuit 2. Thus, the less conductive transistors 20 and 22 on the read path will not unduly impact the ability to write to the data retention circuit 2 from the bit lines which involves forcing a change of state of the data retention circuit 2. Forcing such a change of state of the data retention circuit 2 would be difficult if the pass gates 12, 14 were made insufficiently conductive, thereby impacting the write robustness. It will thus be seen that there is a dichotomy between the requirements of the read operation and the requirements of the write operation in order to achieve robust operation.
While the memory cell of FIG. 1 is able to improve the overall robustness of operation by providing a separate read and write mechanism, it suffers from the significant advantage that the number of transistors within the memory cell has increased from six to eight compared with a standard 6T memory cell. This reduces the memory cell density which can be achieved as well as increasing the power consumption and cost of the integrated circuit memory.
FIGS. 2 and 3 of the accompanying drawings also illustrate known memory cell designs in which the read mechanism has been separated from the write mechanism. These further known memory cell designs also both suffer from the disadvantage of requiring a higher number of dates per sell and the same disadvantages as discussed above in relation to FIG. 1.
It is desirable to be able to provide an integrated circuit memory with increased robustness of operation and which does not disadvantageously increase the number of devices required for each memory cell.